Talks and Poster Presentations (with Proceedings-Entry):

W. Steiner, J. Rushby, M. Sorea, G. Pfeifer:
"Model Checking a Fault-Tolerant Startup Algorithm: From Design Exploration To Exhaustive Fault Simulation";
Talk: IEEE International Conference on Dependable Systems and Networks, Florence, Italy; 06-28-2004 - 07-01-2004; in: "Proceedings of the International Conference on Dependable Systems and Networks (DSN 2004)", IEEE, (2004), ISBN: 0-7695-2052-9.

English abstract:
The increasing performance of modern model-checking tools offers high potential for the computer-aided design of fault-tolerant algorithms. Instead of relying on human imagination to generate taxing failure scenarios to probe a fault-tolerant algorithm during development, we define the fault behavior of a faulty process at its interfaces to the remaining system and use model checking to automatically examine all possible failure scenarios. We call this approach "exhaustive fault simulation". In this paper we illustrate exhaustive fault simulation using a new startup algorithm for the Time-Triggered Architecture (TTA) and show that this approach is fast enough to be deployed in the design loop. We use the SAL toolset from SRI for our experiments and describe an approach to modeling and analyzing fault-tolerant algorithms that exploits the capabilities of tools such as this.

Online library catalogue of the TU Vienna:

Created from the Publication Database of the Vienna University of Technology.